A conventional semiconductor integrated circuit device will be described below. For example, in a semiconductor integrated circuit device such as an LSI (Large Scale Integrated circuit), it is necessary to supply synchronized clock signals to cells such as flip-flops which are laid out on a chip as a whole on the assumption that synchronous design should be performed. This is necessary to prevent an erroneous operation caused by a delay or influence caused by hazard from a combination circuit. More particularly, as a scale and speed of a circuit increases, the precision in the synchronization is regarded as more important.
However, inside the LSI, when clock signals are supplied by a clock buffer and wires, different transmission delays sometimes occur according to the load or wire length of a circuit which is connected in the downstream side. More specifically, as shown in a clock driver circuit in FIGS. 5A and 5B as an example, when single clock signals subjected to buffering by a clock buffer are distributed to, e.g., a plurality of FF (Flip-Flops) shown in a drawing (see FIG. 5A) through clock buffers of a plurality of stages, the clock signal reaches a cell while the clock has a skew (clock skew) caused by the number of stages of the clock buffers and a wire length (see FIG. 5B). When the clock signal has an excessive skew, then a malfunction which accompanies such a skew occurs in the LSI.
Therefore, in the design of an LSI, it is very important to suppress a skew within the range in which a correct operation is performed in order to prevent the malfunction and to adapt to increase in the scale or the speed of a circuit.
FIG. 6 shows an example of the configuration of a conventional LSI. In FIG. 6, reference numeral 101 represents an LSI. The LSI 101 comprises a clock buffer 2, a data input/output buffer 3, a clock input PAD 4, a data input/output PAD 5, a CPU core unit 6, an FPU unit 7, a first random logic unit 8, a second random logic unit 9 and a memory unit 10.
In this LSI 101, a clock signal is input through the clock input PAD 4 and the clock buffer 2 arranged in a peripheral section. In addition, wires are intentionally bypassed to suppress a skew, and wiring control of the clock is performed such that wires extending to all the constituent units are electrically equal to each other in length. In this manner, the supply of a clock signal with a small skew is realized.
FIG. 7 is a chart showing an example of a clock wiring control method in a conventional LSI. This LSI is different from that shown in FIG. 6. In the conventional LSI of FIG. 7, a clock signal is input through a clock input PAD 4 and a clock buffer 2 arranged in a peripheral section, and the clock signals are distributed to respective constituent units by wires extended in the form of a mesh. In this manner, a clock signal having an averaged uniform transmission delay can be input to each of the constituent units, and a skew can be suppressed.
Thus, in the conventional semiconductor integrated circuit device, isometric wiring is performed such that wires extending from the clock buffer 2 to respective blocks are made equal to the length of a wire extending from the clock buffer 2 to the farthest block, so that the clock signal is supplied to each of the constituent units while a skew is suppressed.
However, in the clock wiring control method of the conventional semiconductor integrated circuit device, since the wire extending from the clock buffer to the farthest block is used as a reference, although a skew can be decreased, a transmission delay in the circuit as a whole disadvantageously increases because a length of the wire extending from the clock buffer to a nearer block is long.
In addition, since the wire which extends from the clock buffer to the farthest block is used as a reference, the layout of clock wiring becomes complex. More particularly, a wiring path extending from the clock buffer to the relatively nearer blocks becomes complex. It is disadvantageously difficult to perform wiring control of a clock.